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This work package addresses the study of open issues regarding hardware building blocks and architecture for next generation reconfigurable devices, especially those that are poorly addressed with current reconfigurable architectures mainly based on FPGAs or with limited dynamic reconfiguration capabilities.

The main challenge of this work package is to propose a smart reconfigurable computing hardware carefully crafted for use with methods and tools developed in the "methodologies and tools" work package and covering the requirements of the different application domains.

Unless in some specific and very simple situations, today’s reconfigurable computing platforms cannot be used as the sole computing resources in a given system. In general, reconfigurable resources are used in combination with standard computing resources and other devices in a system. The MORPHEUS architecture, since it has to comply with a broad range of applications, is intended to be a complete platform, serving a complete application domain instead of one dedicated application. The architectural design has been driven by real needs of key application domains, where the subsequent goals have been followed to define a multi-purpose standard platform for reconfigurable compting.

Increased computational efficiency (improved utilization of parallelism)
Increased power efficiency (voltage scaling)
Better flexibility to handle changing requirements
Adaptation to multiple standards (adaptive switching of algorithms)
Sustainability (reuse one architecture for more than one product, maintenance of products in the field.)
Improved time to market and productivity
Opportunity for late changes / upgrade in field
Complexity mastering of heterogeneous systems utilizing different computation models

ARCHITECTURE

The first result of the MORPHEUS project is its architecture made of a control ARM processor with peripheral components: three Heterogeneous Reconfigurable Engines (XPP-III, PiCoGA/DREAM and FlexEOS), a memory hierarchy and common interface for accelerators, an efficient and scalable communication and configuration system. All control, synchronization, and housekeeping is handled by an ARM 926EJ-S embedded RISC processor. It shall be emphasized that the prime task of the ARM processor is to be the central controller for the whole platform.
Computing acceleration is ensured by the three HREs:

The XPP-III is a coarse grain reconfigurable array primarily targeting algorithms with huge computational demands but mostly deterministic control and dataflow.
The PiCoGA/DREAM core is a medium-grained reconfigurable array consisting of 4-bit ALUs.
The FlexEOS is a lookup-table based, fine grain reconfigurable device. It is a kind of embedded Field Programmable Gate Array (eFPGA).

The HREs in general operate on differing clock domains, they are decoupled from the system and interconnect clock domain by data exchange buffers (DEB) consisting of dual ported (dual clock) memories either configured as FIFOs or ping-pong buffers. From a conceptual point of view the HREs can access their input data only from their respective local DEBs. The ARM processor, which is in charge of controlling all data transfers between memories and DEBs or between DEBs, has to ensure the in-time delivery of new data to the DEBs to avoid idle times of the HREs.

Figure 1: The MORPHEUS chip architecture

Scalability of the MORPHEUS platform: It is important to emphasize that the MORPHEUS platform architecture has to be understood only as an architectural framework. The platform only defines which modules can be part of the architectural approach and how they can be integrated. Since the platform itself is defined in a modular and scalable fashion, customized architectures for various specific applications can be derived. In every case, before MORPHEUS technology can be used, a customized architecture must be derived from the platform. The process of customization allows the tailoring of the architecture for the specific application requirements.

TECHNICAL BACKGROUND KNOWLEDGE

a - Control and (dynamic) reconfiguration concept

Up to now, requirements of embedded computing solutions (cost, mobility, functionalities) are typically translated by designers in area, energy and performances constraints and thus often lead to the specification of dedicated chips. In the same time, the explosion of the cost of development results in the need for flexible architectures taking advantage of high-level programming tools.

Within this framework, static reconfiguration is used to adapt the architecture to the application. Then, computing resources and communications can be configured according to the application requirements.
However, performances, energy constraints and low cost demand a clear breakthrough which can only be achieved through a stronger adaptation of the architecture to the application. For this purpose, dynamic reconfiguration is compulsory. It enables to optimise the architecture “on the fly” taking into account the current pattern of calculation, to implement either loop kernels, pipeline stages or taking advantage of data locality. Such kind of reconfiguration is only relevant if and only if mechanisms are established to speed the reconfiguration process.

b - Modularity

Modularity is a key aspect of the MORPHEUS approach. Architectural concepts, as already researched by several partners are quite heterogeneous. This is a huge opportunity if these differing architectures become scalable and modular. Another important aspect of modularity is the possibility to easily integrate the scalable and modular block into one architecture. For this reason generic interfaces have to be provided by the modules.

It is denoted in Figure 1 that the definition of interfaces for logical and physical interconnection of the modules integrated into the reconfigurable architecture is one of the main challenges of this workpackage.
The link of this modular HW platform with the toolset should be ensured by “tool-interfaces” providing the important aspects and requirements like simulation, debugging, verification and monitoring.

c - Architectures for coarse and fine grain reconfigurable computing

Coarse-grained reconfigurable architectures fill the gap between General Purpose Processors (GPP, DSPs) fine-grained FPGAs specialized hardware (ASICs). Reconfigurable architectures are flexible and provide a high degree of parallelism. They are built from a large number (typically in the range between 10 and 100) of processing elements with ALUs for signal processing algorithms. Applications are mapped for a certain time to the array while data flows through the network of operators (i.e. ALUs). After a certain number of data has been processed, the array can be reconfigured, thus the functionality of the nodes and the interconnection network is changed. This approach is well suited for streaming data with limited control flow. It is the intention of the project to improve the application space towards more control-flow oriented architectures. A more flexible coarse grained architecture needs to communicate very efficiently with the steering unit – typically a GPP - and must be integrated with low latency into the memory hierarchy (including dynamic reconfiguration). Coarse-grained architectures are designed for algorithms operating on word-level (e.g. 16 bit). However several algorithms (e.g. Entropy encoder in video codecs) are demanding fine-grained architecture such as FPGAs. Though eFPGAs are not in the focus of the project, we will utilise legacy eFPGAs in the SOC and will design efficient interfaces to the coarse grained architectures. Thus, if the algorithm was properly partitioned each of the architectures can operate in its optimal application space. The benefit is a better ratio of area vs. performance for the overall application without sacrificing flexibility.

d - Efficient interconnection infrastructure

While fine- as well as coarse-grained IP has progressed significantly during the last years, the resulting requirements on interconnect in terms of bandwidth, flexibility and efficiency have hardly been targeted by reconfigurable architecture research. Especially the huge opportunities of run time reconfiguration of interconnect are only marginally exploited so far. In order to do so, today’s dominant bus architectures need to be extended by reconfigurable high bandwidth point to point connections as well as suitable network-onchip (NoC) approaches. The heterogeneous and mixed-grain SOC architecture with its different possibilities to run tasks on the chip and also the flexibility for tasks to be migrated from one architecture tile to another forces to integrate a high performing and adaptive interconnection infrastructure. For this a run-time adaptable network with the possibility of changing the topology and protocol, e.g. exploiting also dynamically the trade-offs between packet and circuit-switched communication parts/phases, has to be developed and synthesized. In addition, the connection of the different cores with parallel memory modules has to be considered. To provide a fast data-throughput it has to be enabled, that bottlenecks for parallel memory access and inter-tile communication have to be avoided. To exploit the parallel mixed-grained architecture efficiently it is necessary to integrate more than one memory module connection resulting in determining a suitable trade-off in central/decentral (e.g. global/local) memory access interconnect topologies.

e – Memory topologies

Since reconfigurable SOC offer the potential to drastically increase processing power and efficiency especially in data oriented processing schemes, the bottleneck is passed on to the simultaneously growing requirements on the respective memory infrastructure. Intelligently organized on-chip memories – configured as local memory with user controlled DMA access or as transparent cache – become mandatory, because off-chip solution lack the required bandwidth and are unacceptable regarding power consumption and system costs. In addition memories in reconfigurable SOCs pose special challenges to the digital designer, since typical applications often require certain flexible access patterns (e.g. different word sizes, parallel access or different addressing modes). Hence, on-chip memories are probably the most mission critical components of today’s embedded signal processing systems. Generalized solutions and methodologies are not yet state of the art. It is one goal of the MORPHEUS approach to develop such methodologies and to extend the huge opportunities of (dynamic) reconfiguration to the memory infrastructure.