Links
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Application to the ICT 2008 event on 25-27 November 2008 in Lyon, France
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MORPHEUS presentation at VLSI SoC 2008 conference October 13-15 Rhodes Island, Greece.
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MORPHEUS-AETHER Autumn School and Workshop Oct 7-9 2008 in Lugano, Switzerland.
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RAW 2008,15th Reconfigurable Architectures Workshop. April 14-15, 2008. Miami, Florida, USA.
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MORPHEUS at DATE 2008 Munich, Germany 10-14 March 2008.
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Two papers at SYMPA08 conference. Fribourg, Switzerland, Feb. 11-13 2008.
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MORPHEUS presentation at CASTNESS, Rome, Jan. 16 2008.
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MORPHEUS presentation at the 4S final workshop, Prague Dec. 6 2007.
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Special session on MORPHEUS at SoC 2007, Tampere Finland November 19-21 2007.
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MORPHEUS-AETHER Autumn School and Workshop Oct 8-11 2007 in Paris.
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Invited Talk at ERSA 2007, June 25-28 2007, Las Vegas, Nevada, USA
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MORPHEUS  project  at  DATE April 16-20 2007 presents  in regular sessions, at the University booth and in workshops.
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MORPHEUS PRESS RELEASE
European project on course to develop a leading edge solution for embedded computing.
Released on March 26 2007.
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Intranet THALES press release, March 07 2007.

CASTNESS 2008

CASTNESS'08 15-18 January 2008 - ROMA - Italy

Computing Architectures and Software Tools for Numerical Embedded Scalable Systems

Presentation by P. Bonnot MORPHEUS project overview and focus on THALES needs and solutions

CASTNESS 2007
Within he context or the AETHER project about
Self-Adaptive Embedded Technology for Pervasive Computing Architectures the MORPHEUS project particepated to the organized event named CASTNESS.

Presentation by P. Bonnot Thales TRT
 
Application Programming design flow for the Morpheus heterogeneous dynamically reconfigurable platform.

Contents of the presentation

The contribution from the MORPHEUS project was focused on the global toolset. This technical presentation introduced the MORPHEUS project, illustrating its goal to implect partnment a reconfigurable architecture chip and related toolset and listing the projeers. It presented the MORPHEUS execution model showing the system architecture made of reconfigurable processing elements, memories, general purpose processor, configuration manager and interconnection infrastructure. The presentation analyzed also the data flows for computation, control, configuration and reconfiguration. A programming model was presented where the user can model in C language the accelerated tasks. The programming environment is based on two parts 1) the sequential C-based description of the application 2) the graphical parallel description of the accelerated function (plus the C kernels). All main parts of the flow have been described in detail: the retargetable compilation based on the MOLEN paradigm, the control of reconfiguration added to eCos OS and the synthesis of accelerated functions from SPEAR/CASCADE and MADEO.




 
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