DATE 2007 conference was held in Nice, France, April 16-20 2007.

DATE is the largest electronic system design and test conference in Europe. As part of the conference, a university booth was organized for EDA software and hardware demonstrations. The conference provides different kinds of events like university booths, workshops and regular paper sessions.  This edition of the conference included a rich  set of presentation about the  MORPHEUS  project.

Paper "A programming toolset enabling exploitation of reconfiguration for increased flexibility in future system-on-chips".
Authors: G. Edelin, P. Bonnot, W. Gouja,K. Bertels, F. Thoma, A. Schneider, J. Knäblein, B. Pottier, J.C. Le Lann
This paper presents an integrated programming toolset for application implementation of a heterogeneous reconfigurable architecture. The objectives of the toolset are to optimize the application implementation productivity and to enable the dynamic reconfiguration on reconfigurable units of the target architecture. The proposed solution is based on the combination of a compilation concept permitting to call function implemented on these reconfigurable units, an operating system dynamically managing the units’ reconfigurations, a formal specification tool and a design tool for the implementation of the accelerated functions. The paper gives an overview of these tools, which are combined to take benefit of their facilitated reciprocal interactions.

Paper “A dynamically adaptive DSP for heterogeneous reconfigurable platforms”
Authors: F. Campi, A. Deledda, M. Pizzotti, L. Ciccarelli,C. Mucci, A. Lodi, A. Vitkovski, L. Vanzolini
This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero overhead for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm2, 0.2GOPS/mW) and relatively small area occupation (18 mm2), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages.
 
Paper “Implementation of AES/Rijndael on a dynamically reconfigurable architecture”
Authors: C. Mucci, L. Vanzolini, F. Campi, A. Lodi, A. Deledda, M. Toma, R. Guerrieri
Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. In this paper, we present the design of AES/Rijndael on a dynamically reconfigurable architecture. We will show a performance improvement of three orders of magnitude compared to the reference code and up to 24× speed-up figure with respect to fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, we show better energy efficiency with respect to the other programmable solutions, obtaining up to 3 Mbit/sec/mW

Presentation from Alcatel-Lucent and CUT entitled:

"Ethernet based in-service reconfiguration of SoCs in telecommunication networks"
Authors: Sebastian Goller, Uwe Pross, Ulrich Heinkel, Marcel Putsche (CUT)
         Axel Schneider, Joachim Knaeblein, Bernd Müller (Alcatel-Lucent)


Presentation at the DATE University booth - System Exploration track "MORPHEUS: Multi-purpOSe dynamically Reconfigurable Platform for intensive Heterogeneous processing"
Authors: Mattias Kühnle, Florian Thoma, Michael Hübner, Jürgen Becker,University of Karlsruhe - Germany
The European MORPHEUS project addresses a technology breakthrough for embedded computing by developing a reconfigurable platform and the corresponding toolset. MORPHEUS copes with the challenges of rising complexity and the enlarging design productivity gap by developing a global solution based on a modular heterogeneous System-on-Chip platform providing the disruptive technology of dynamically reconfigurable computing including completed by a software oriented design flow and a consistent toolset. MORPHEUS strives to establish the European foundation for a new concept of flexible “domain focused platforms”, which are positioned between general purpose flexible HW and general purpose processors, and provide breakthroughs in performance and cost-effectiveness for embedded computing systems. This three-year project will finally provide a modular silicon demonstrator in 90nm technology composed of complementary run-time reconfigurable building blocks on which four complementary test-cases will be mapped.

Date 2007 provides for EDA software and hardware demonstrations unique chance to exhibit protptypes to Academia and Industry, open to demonstrate the pre-commercial results obtained in government founded projects.

DATE Workshop: "Directions in FPGAs and Reconfigurable Systems: Design, Programming and Technologies for adaptive heterogeneous Systems-on-Chip and their European Dimensions"
Organized by J. Becker, University of Karlsruhe - Germany
Due to the increasing number of integrated transistors in future System-on-Chips, novel tools and methods for dealing with the increased complexity must be investigated. Several projects sponsored by the European Commission develop complex heterogeneous and reconfigurable SoC architectures e.g. 4S, MORPHEUS, AETHER, SHAPES, SARC and HARTES. The run-time optimal functional execution is a strong motivation for heterogeneous architectures and the possibility of dynamic and partial hardware reconfiguration enables a higher degree of flexibility and run-time adaptivity.
The hardware architectures of such systems must be optimized for allowing a self-adaptive behaviour of the system with a high degree of flexibility while still allowing a simplified programmability. The architecture must be designed with redundant components and dynamically self-optimized in terms of power consumption, performance and resource allocation. In many cases the complete architecture includes reconfigurable analogue tiles, reconfigurable digital processing accelerators and run-time adaptive controllers. Of course, the memory architecture in such a system will become a critical point and innovative memory constellations for reconfigurable systems are also investigated within the research programs. Since reconfigurable systems require storing functional descriptions for dynamic configuration, minimizing the time to fetch and configure a function dynamically will be important for the system real-time response.
For such heterogeneous architectures it is required to develop tools for early system simulation and evaluation since the design space is multi-dimensional and the requirements of the environment are not predictable. The different approaches must allow components from multiple architectures as well as different constellations of the network interface to be tested and verified in a common workspace. The network is important in order to enable IP based design on a heterogeneous architecture. In order to fully exploit such architectures the dynamic configuration of the network is an important feature that affects the system performance of the system. Naturally, early verification of this kind of network will be critical for the future exploitation of heterogeneous architectures.
Another important consideration is the programmability. The application developer should be able to model the applications on a high level without a detailed knowledge about the underlying hardware/software architecture. The tools and possibilities for run-time adaptation should then enable the most optimal run-time system configuration. This Workshop aims at joint discussion about these topics with the representative partners from all over Europe fostering inter-project cooperation and advisement.

The workshop contained a presentation from G. Edelin about the MORPHEUS project: "Exploitation of reconfiguration for increased run-time flexibility and self-adaptive capabilities in future SoCs". See also the corresponding paper entitled: "A programming toolset enabling exploitation of reconfiguration for increased flexibility in future system-on-chips" The picture shows the poster of about MORPHEUS that we presented at the booth.

Special session on “Reconfigurable Computing: Architectures, Tools and Applications
Organized by J. Becker, University of Karlsruhe - Germany
This contribution to the dissemination in DATE 2007 is a tutorial about reconfigurable computing. The presentation performs an analysis of the trends in ASIC and ASSP design motivating the trend toward run-time adaptive hardware architectures. It examines today’s fine grain devices architectures (Xilinx Virtex-II) application and technology mapping. New coarse and multigrain approaches are introduced, as the HoneyComp architecture. A new set of reconfigurable architectures is examined which are developed in European projects: ÆTER, 4S and MORPHEUS. An overview of the MORPHEUS project is provided explaining its motivations. Today’s embedded systems demand computing performance, cost-efficient development and functional flexibility. MORPHEUS designs a modular SoC platform considering dynamically reconfigurable computing and software oriented design flow. The goal is to achieve design improvements in terms of Gops/Watt and more computing flexibility as well as design reuse capabilities and time to market improvements.
Presenting the status of the activity, a picture is provided about the principles and paradigms for system management methodology and tools. Now the specification of dynamic reconfiguration services and the evaluation of hybrid scheduling approaches are complete. The next steps are the eCos porting to MORPHEUS architecture extending the operating system to cope with heterogeneous reconfigurable technologies and dynamic reconfiguration.
The architecture of MORPHEUS is shown, presenting the present status where we developed a common simulation environment using SystemC, CoWare and ConvergenSC. The next steps are the refinement of the SystemC model, the adaptation of the simulation environment to support the needs of the applications, the HDL coding of the components, their integration with the NoC and finally the backend design.

DEMONSTRATION - TUD and ACE demonstrate MOLEN and the Power PC for Virtex-II FPGA platform.
ACE's main dissemination activities in 2007 took place between 16 and 20 April, 2007, at the Design, Automation and Test Europe (DATE 07) in the Acropolis convention center in Nice, France. Together with MORPHEUS partner TU Delft and other academic partners, ACE held a dedicated exhibition stand focused at presentation and demonstration of academic compiler research projects. At this academic compiler research booth, TU Delft presented and demonstrated the preliminary MORPHEUS result: the CoSy based MOLEN compiler.