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Date 2008 conference.

THALES is presenting a paper entitled "Definition and SIMD Implementation of Multi-Processing Architecture Approach on FPGA"
Autors: Ph. Bonnot, G. Gaillat et al, 13/3/2008.

The DATE 2008 friday workshop (14/3/2008) entitled “The Run-Time Reconfigurable and Heterogeneous MORPHEUS Platform” will be presented by Ph. Bonnot.

ARCES, ST, UK, THALES are presenting a paper entitled "Design of a HW/SW Communication Infrastructure for a heterogeneus reconfigurable processor".

Abstract: Reconfigurable architectures and NoC (Network-on-Chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of a new heterogeneous reconfigurable SoC. This SOC integrates units of various sizes of reconfiguration granularity. Moreover, the included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. Spatial and sequential design capabilities of the toolset permit mapping and execution of the target applications. The toolset involves compilation optimization techniques to schedule macro-operand level instruction configuration and execution making benefit of a set of dynamic reconfiguration services. Micro-operand level instructions accelerated on reconfigurable units are designed thanks to data-parallelism mapping and high level synthesis techniques.
On a reference CMOS090 implementation the described interconnect infrastructure is works at the system reference frequency of 200 MHZ sustaining the run-time bandwidth required by the different HREs, requiring a share of 5% in area and <1% in power consumption wrt the overall SoC.

Arces and ST are presenting a paper at DATE'08 on the implementation of LFSR-based applications (e.g. CRC, Scrambler) on DREAM/PiCoGA.

Title: "Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array"

Authors:
C.Mucci, L.Vanzolini, I.Mirimin, D.Gazzola, A.Deledda - ARCES, University of Bologna L.Ciccarelli, F.Campi - STMicroelectronics

Abstract: Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptography, digital braodcasting and communication. High-throughput demands require highly parallel implementations, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Although this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of parallel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined devices usually provide better performance, e.g. in term of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ethernet standard that achieve on the target architecture up to ~25 Gbit/sec
throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices.

University of Technology Chemnitz and Alcatel-Lucent are pesenting a paper entitled "A Prototype of reconfigurable Network Application"

Authors: Uwe Proß, Sebastian Goller, Marko Rößler, Ulrich Heinkel,
Axel Schneider, Joachim Knäblein

Abtract: High-end telecommunication network technologies are underlying a rapid evolution. On the one hand, newer network technologies and standards provide often better bandwidth utilization and a higher quality of service. Network providers are interested in an early adaption of new technologies and standards for optimal network exploitation. This requires manufacturers of telecommunication equipment to develop rapidly and implement early the new technologies. On the other hand, long lasting standardization processes force manufacturers into risky development strategies, since an early time to market collides with probably unstable network standards. This causes high business risks. Design re-spins and updates of the network devices resulting from this situation can cause enormous costs. Since the overall situation cannot be changed, a solution is required which lowers the development risks. In this paper, we present the implementation of a prototype of an ethernet node, which can be dynamically reconfigured using the ethernet protocol. The ethernet node is a prototype of a later application on the MORPHEUS platform in order to show the capabilities of SoCs with embedded reconfigurable technologies. The implemented application is a reconfigurable network node based on the ethernet protocol. The overall goal is to develop a system that can monitor the data stream received via ethernet and identify reconfiguration data on the basis of the EtherType field in the ethernet header. The reconfiguration data is then extracted from the datastream and stored in a memory. After the complete data stream has been received and no transmission errors have been found by checksum calculation the reconfiguration of the network node starts. For demonstration purposes, the node is implemented on a prototype platform consisting of two Xilinx boards (XUP Development Board).
These boards feature a Virtex-II Pro XC2VP30, an ethernet interface including an onboard PHY, a RS232 interface and onboard DDR RAM (256 MB). Since the prototype platform emulates an embedded FPGA placed on an ASIC it has been divided into corresponding parts. The first board emulates the embedded FPGA macro and contains an ethernet MAC. The MAC receives the ethernet data stream generated by an external PC. After receipt the
content of the ethernet packages is checked for reconfiguration data by checking the EtherType field of the header. In case a reconfiguration packet has been identified, the payload of the package is copied from the data stream and sent to the second board via RocketIO. The reconfiguration data received on the second board is stored in the onboard DDR RAM. After the complete configuration stream has been received the PowerPC core on the second board is used to calculate the CRC of the configuration stream. If no errors are detected, the reconfiguration of the XC2VP30 on the first board is initialized. The success of the reconfiguration is shown by fixing an initially faulty ethernet MAC. Ethernet packets contain a CRC32 checksum to verify their payload. This CRC32 calculation produces wrong results in the initial ethernet MAC. To make this error visible, all received ethernet packets are sent back to its source. The CRC32 calculation error is detected by the PC by receiving incorrect ethernet packets. After reconfiguration, the CRC32 error is fixed. The MAC can be monitored and controlled by the PowerPC core, which is implemented in the XC2VP30. The software running on this core provides access to all registers of the MAC. A separate RS232 connection between the external PC and the board allows an ethernet independent communication so the functionality of the MAC can be checked even if the ethernet connection has a malfunction.

MORPHEUS integrated toolset, presentation at the university booth.
Florian thoma, Matthias Kunle, Michael Hubner, Jurgen Becker, Klaus D. Muller-Glaser. Universitat Karlsruhe (TH) Germany

The European MORPHEUS project addresses a technology breakthrough for embedded computing by developing a reconfigurable platform and the corresponding toolset. This paper details the integrated toolset.
MORPHEUS copes with the challenges of rising complexity and the enlarging design productivity gap by developing a global solution based on a modular heterogeneous System-on-Chip (SoC) platform providing the disruptive technology of dynamically reconfigurable computing including a software oriented design flow and a consistent toolset. The toolset supports retargetable compiling, spatial design and dynamic control.

Flexim Real-time Digital Film Processing with a FPGA-based Reconfigurable Platform, presented at the university booth.