ECSI WORKSHOP on reconfigurable system on chip

Future ASIC-based SoCs will have to cope with increasing challenges rooted in application-driven requirement (e.g. changing standards) or manufacturing problems. This might lead even for traditionally ASIC-based SoCs to resort to reconfigurable computing. The workshop covered in a dedicated session industry needs and requirements to understand current and future application scenarios for reconfigurable systems in their various flavors and domains. The efficient integration of reconfiguration in SoCs requires powerful design tools. Hence an overview to existing and future EDA support for reconfigurable Systems-on-Chip is discussed.

The MORPHEUS partners presented four invited talks: RESEARCH ACTIVITIES "Application programming design flow for the MORPHEUS dynamically reconfigurable platform" Philippe Bonnot, Thales TRT J. Becker,  “Dynamic Reconfigurable Hardware – Tools and Architectures for SoC” J. Becker, University Karlsruhe INDUSTRY  NEEDS REQUIREMENTS "Reconfigurable Computing Needs from an Industrial  Perespective" Stelios Perissakis, INTRACOM "Applications for Reconfigurable Systems-on-Chip in Telecommunication Networks" Axel Schneider, Alcatel-Lucent Technologies

Contents of the presentations

·       Application programming design flow for the MORPHEUS dynamically reconfigurable platform
The contribution from the MORPHEUS project was focused on the global toolset. This technical presentation introduced the MORPHEUS project, illustrating its goal to implement a reconfigurable architecture chip and related toolset and listing the project partners. It presented the MORPHEUS execution model showing the system architecture made of reconfigurable processing elements, memories, general purpose processor, configuration manager and interconnection infrastructure. The presentation analyzed also the data flows for computation, control, configuration and reconfiguration. A programming model was presented where the user can model in C language the accelerated tasks. The programming environment is based on two parts 1) the sequential C-based description of the application 2) the graphical parallel description of the accelerated function (plus the C kernels). All main parts of the flow have been described in detail: the retargetable compilation based on the MOLEN paradigm, the control of reconfiguration added to eCos OS and the synthesis of accelerated functions from SPEAR/CASCADE and MADEO.

Dynamic Reconfigurable Hardware – Tools and Architectures for SoC
Motivations for run-time reconfigurable architectures are adaptation to changing standards, need to cope with manufacturing problems and run time error correction. Why should we resort to dynamic/partial reconfiguration when full-parallel and semi-parallel implementations are feasible in ASIC design also? Because dynamic/partial reconfiguration allow better trade-off of performance/power-consumption/cost and hardware/software partitioning. Reconfigurable architectures are driven by considerations about area, power consumption and throughput. A fundamental choice is the granularity, linked to the complexity of reconfigurable cell; other important issues are the communication scheme (Bus based or NoC) and the heterogeneous nature of the SoC. Among the fine grained run-time reconfigurable architectures a FPGA Based on-demand reconfigurable Systems is presented in the automotive domain. Another architecture based on FPGA is a two Layer Reconfigurable System called QUKU which is a Coarse Grained PE array on FPGA fabric (Reconfigurable on two layers),it aims at combining the bests of both the worlds. As examples of coarse grained run-time reconfigurable architectures the Digital On-Demand Computing Organism and the HoneyComb Architecture are presented. Finally three examples of mixed-grained run-time reconfigurable architectures are shown from the ÆTHER, 4S and MORPHEUS projects. Justification is given for the MORPHEUS project meeting today's embedded systems demand in computing performance, cost-efficient development and functional flexibility and sustainability.  It is conceived to face the design-productivity gap due to the increasing complexity of the platforms. MORPHEUS develops a modular SOC platform considering dynamically reconfigurable computing software (SW) oriented design flow. The goals are to improve density and computing flexibility, design reuse and time to market. The applications implemented in silicon will be mainly focused on professional video and wireless routing. The basic system management methodologies and tools are described including the principles and paradigms for management of reconfigurable computing. An overview of the MORPHEUS architecture is provided, describing also the simulation environment in SystemC.

Reconfigurable Computing Needs from an Industrial Perspective
This talk introduces the needs for reconfigurable computing, from an industrial perspective. It describes the general settings and objectives of MORPHEUS and the applications. The role of MORPHEUS is to develop a reconfigurable computing solution resorting to a few key technologies. One is the ability to provide a mix of fine-, mid-, and coarse-grain fabrics; it is fundamental for best fitting the performance needs of diverse applications. Locally synchronous, globally asynchronous design (using a NoC) is used to manage the complexity of the design separating computation and communication. The most peculiar technology is dynamic reconfiguration, it enhances the platform flexibility. Another key aspect of the project is that it develops a high-level programming methodology and the corresponding tools.

The MORPHEUS architecture is based on 3 acceleration engines: XPP-III coarse grain reconfigurable core, PiCoGA multi-context, mid-grain array and FlexEOS embedded FPGA macro. Data among the acceleration engines is exchanged through a Network-on-Chip, two more AMBA AHB buses are used for the configuration and the IO data. An ARM9 controls the application. A hardware block is developed for control of reconfiguration. The architecture is completed by other blocks: a DMA control, SRAM/DRAM controller, on-chip SRAM and IO interface/peripherals.

MORPHEUS is driven by 4 applications from different domains: networking, intelligent cameras, high definition video digital film processing and broadband wireless telecommunications. They present common characteristics. A software implementation is not sufficient because high performance is required. Flexibility is important, fixed hardware such as ASIC is not appropriate. All the applications imply low to medium volumes, so ASIC is not appropriate from cost standpoint. Power dissipation is important but not critical; all devices can be mains-powered. The chosen target applications, by leveraging on a mix of different computation granularities and exploiting dynamic reconfiguration, can benefit from the new MORPHEUS architecture better that from a common FPGA. Reconfigurable computing appears ideal for those 4 applications.

The first one is a network application developing a SoC for network protocol processing at high data rates. The main characteristic is that it must be able to reconfigure over the network.

A second target application deals with intelligent cameras. It extracts high-level information from sequences of images: a functionality that can be used in industrial automation, surveillance and traffic control. Such cameras should have capabilities for low level and high-level image processing implying understanding and communication. Intelligent cameras need high computational complexity in the order of Gops to teraops for real time processing. The application is largely dominated by byte-/word-level pixel operations and applies a wide range algorithms switching among operating modes (event detection, event tracking, object identification).

The digital film processing application involves high processing workload, it must handle rates from 350 Mbps to 4.5 Gbit/s for current image formats and much higher requirements in the future. It performs a mix of coarse-grain operations for pixel-level processing and fine-grain operations (compression). It requires high communication bandwidth and/or storage. Phased introduction of features is desirable for early time-to-market and on-demand, in-the-field upgrade of features. Also necessary is the possibility to have a dynamic selection of the algorithm to apply (action scene vs slow camera, pan vs scene change).

The final application is a broadband wireless communication. The targets are the next-generation mobile WiMAX networks supporting multihop communication (IEEE 802.16j). This standard introduces a new entity: the Multihop Relay Station. This broadband wireless application has high performance requirements (ex. 3 Gops byte-level for 16 Mbit Viterbi decoder). Most computations are coarse-grain (typically 16-bit complex), FEC is largerly at bit-level (convolutional coding, interleaving). The application needs reconfigurability to be flexible with respect to standards (deploy early, extend lifetime) and for switching modes it needs on-the-fly reconfigurability. The relay station is part of the network infrastructure, but it is supposed to be low cost (much lower than the base station).

Applications for reconfigurable systems-on-chip in telecommunication networks
Market trends are evolving towards the “all-IP” network. New services drive technical innovation imposing more differentiation to service providers. Consumers’ service choices are growing: 57 million in U.S. read blogs, 6 million users have signed up with Skype, 20% or more of 3’s subscribers watched its World Cup mobile TV service each week, Crazy Frog generated £40 million in ringtone revenues in 2005, Judson Laipply’s clip was viewed 31 million times in four months on YouTube. The user base becomes fragmented making the “killer application” much less likely.

Designing the network of the future will face many technical challenges to meet the end-user expectations. Many protocols need to interoperate in a converged network, requirements are demanding and early market presence of innovative products is the key for successful business. Telecommunication systems need to meet ambitious performances and power requirements, while providing a high degree of flexibility for updates.

Reconfigurable systems-on-chip can provide a fundamental contribution to meet the user expectations facing the technical challenges of high-end telecom systems. With traditional hardware/chip platforms for high-end telecom systems all the requirements are covered by two distinct sets of platforms: requirements abut flexibility, time to market and product life cycle is met by FPGAs, DSPs and NPs; requirements about cost and performances are met by ASICs and ASSPs. With the introduction of reconfigurable systems-on-chip for high-end telecom systems the same platform will be able to cover all the requirements.

Alcatel-Lucent is interested in updating particular hardware function in an ASIC architecture and developed a concept for updating the hardware of installed network elements partially. The reason for updating could be adaptation to standards or bug fixes. The hardware functions which are likely to be updated must be selected carefully and allocated to an embedded FPGA. In a first phase of the project a demonstrator based on two FPGA evaluation boards is built in order to proof the concept. In phase 2 the application is ported to the MORPHEUS platform. For demonstration purposes the well known Ethernet functionality has been chosen for implementation. Ethernet data optionally contains reconfiguration data, which is marked e.g. by using a specific IP address. Normal Ethernet data is routed along the system data path. Reconfiguration data, however, is collected packet by packet in a configuration RAM until it is complete. After a consistency check (CRC) is done successfully, reconfiguration is executed under the control of the reconfiguration controller module.