MORPHEUS application for the ICT 2008 event on 25-27 November 2008 in Lyon, France.

The proposed demonstration will show a prototype toolset for programming an heterogeneous reconfigurable architecture. Some application examples will be provided and visitors will be able to test modifications of those examples.

This demonstration is an intermediate result of the FP6 IST MORPHEUS (027342) project after almost three years of developments.

Reconfigurable technology provides simultaneously high computing performance density and flexibility. However, controlling such components integrated within a system level architecture is generally difficult to handle. Moreover, programming reconfigurable components is often difficult because it usually requires hardware design skills.

The toolset proposed within the project provides an easy to use interface to control the acceleration of critical sections of applications on reconfigurable technologies from a system programming point of view. That is to say that all the burden related to setting up the configuration, calling the accelerator, managing data exchanges and synchronising several accelerators is managed by the compiler thanks to this interface.

Also, the design of the accelerated part of the application on the reconfigurable unit is supported by the proposed toolset. That is to say that a graphical interface permits to describe the accelerated function in a manner that helps to express and exploit the inherent parallelism from which high performance can be obtained.

The proposed toolset approach is notably based on a programming model that consist in inserting pragmas in the C code of the application to identify the functions that have to be accelerated on the reconfigurable units. The management of the acceleration at system level is then performed through specific operating system services developed to handle the dynamic reconfiguration.

The design of the accelerated function itself uses a graphical capture interface ensuring the good management of data blocks, corner-turns, etc. The correct logic of interconnection and data reorganization between elementary processing function is automatically generated. These elementary functions are also provided in C code. The tool then generates code for the various technologies.

This toolset is developed to program the chip that is also developed during the project. The realisation will be done on a 90 nm technology after the tape-out that is planned in October this year (thus just before the ICT event). This chip is build around an heterogeneous architecture with a NOC making the interconnection between 3 different reconfigurable units using 3 different reconfigurable technology grains (from fine grain to coarse grain). Each of the 3 technologies is provided with its own tools with different programming interfaces that will be included and homogenised in the presented toolset.