MORPHEUS (IST-4-027342) WP4 PLATFORM
INTEGRATION AND
MONITORING
Outline and Objectives
WP4 is structured in two different phases (18 months each). In
the first phase, WP4 will provide monitoring of the MORPHEUS roadmap
with early assessment of expected results and a constant comparison
with respect to the evolving level of state of the art in research and
industry. This monitoring process is key for adjusting the second
phases to the lessons learned from the first developments and
validation and to the evolution of state of the art in both
architectures and tools. The roadmap revision will be done in
collaboration with the scientific council so that the final goals and
Workplan are refined to maximise the output of the MORPHEUS project.
The check point at the end of Phase 1 guarantees that the
final system will be the best match between the output of WP3, the
implementation constraints and the exploitation plan as it will be
developed at that point.
The existing tight relation between M2000, PACT, ARCES and ST (several
silicon prototypes and products have already been designed and
successfully implemented by ST with IPs coming from these partners)
guarantees the alignment of the technologies, design conventions and
verification flow. More on the implementation issues, there will be a
final revision of the output of WP3 in order to guarantee correct
implementation, viability and consistency of the MORPHEUS solution.
All the above activity is structured in Task 4.1 that will run
during the first 18-months of the project.
Phase 2 includes the design and implementation of the final
silicon and the design and implementation of the final board-level
system including the silicon prototype. The board level activity will
be driven by and application partner (DTB).
More in detail, phase 2 includes the design of the target
platform and of its component including reconfigurable IPs, its
validation with best-in-class verification methodology (including
hardware emulation), the fabrication of the silicon prototypes, testing
and the development of a demonstrator board.
In summary the objectives of WP4 are:
- Monitor the MORPHEUS roadmap in the first 18 months and
expected results
- Monitor state of the art evolution in the first 18 months
- Provide a revision of the roadmap for the second phase (if
needed)
- Review of the WP3 outputs and guarantee implementation
feasibility
- Design and verify the MORPHEUS SOC
- Provide silicon prototypes and application board
A close collaboration is established between work packages 2, 3 and 4
through cross-participations.
Challenges
Monitoring refers to matching the architecture developments with
opportunity and feasibility analysis. As the project addresses
ambitious breakthroughs in an emerging domain of computing with
competition and unbelievable technology progresses, it has to deal with
technical risks and must keep on the state of the art track. This will
be done by continuous assessment of the architecture developments with
respect to the most promising exploitation opportunities. This activity
involves the evaluation of available applications in the Consortium and
participants organizations.
The challenge of designing and reducing to practice an efficient and
viable architecture as result of the analysis of WP3 is in the correct
development and implementation of reconfigurable IPs, the system
infrastructure including connection to external memories and specific
I/O protocols. SoC integration
challenge involves handling the system design database with consistency
with the different IPs views (frontend, back-end, models, etc…).
Monitoring the physical integration and validation phases of such a
complex device has to be considered also a challenging task.
Reconfigurable IPs
The development and implementation of reconfigurable IPs in line with
the outputs of WP3 is a key process of the MORPHEUS program. Partner
will be designing and developing reconfigurable IP solutions targeting
90nm or more advanced silicon process. In particular fine-grain
reconfigurable fabrics and processor-based reconfigurable approaches
require a remarkable amount of full-custom design skills. The partners
involved in designing and developing reconfigurable IP solutions are,
in addition to ST, M2000, PACT, UNIBO/ARCES.
System Infrastructure
The design of the system infrastructure implies the integration of the
MORPHEUS reconfigurable computational core within a system context that
guarantees compliancy with industry standards, I/O protocols, memory
interfaces, industry-standard control processors (like ARM). An example
of this kind of integration is depicted in the following block diagram
where the reconfigurable engines are in the shaded box, while the
surrounding environment provides memory access, ARM9 programming
environment,
dedicated I/O systems. It is just mentioned as an example to
illustrate where the MORPHEUS reconfigurable platform could be inserted
in a global platform. The modular MORPHEUS concept is depicted in
Figure 1. This concept encompasses the openness of the platform
according to the application
requirements : it will be defined in the WP 3.1.
Figure
1 target architecture
Design
and Verification in
nanometer silicon technology
Design and verification of complex reconfigurable structures in 90nm
(or 65nm) silicon technology is a big technical issue. Quality of
results is important to ensure that the final solution will have proper
exploitation and wide adoption. This is particularly true when
prototyping reconfigurable system that have historically shown
acceptance concerns mostly on efficiency and viability rather than on
performance.
System verification will be one of the most critical activities as the
MORPHEUS system joins together all verification problems of field
programmable logic and microprocessor. We expect the effort of
functionally verifying such systems will require the development of
specific methodology and usage of best-in-class and fastest
verification tools like HW emulation and formal methods. The
verification methodology developed in MORPHEUS will be deployed by the
generation of a specific deliverable.
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