BRASS Berkeley Reconfigurable Architectures System and Software. The BRASS group developed the GARP chip for reconfigurable processing as well as the SCORE (Stream Computation Organized for Reconfigurable Execution), a stream-based computer model which virtualizes reconfigurable computing resources and the Pleiades project that seeks to achieve ultra-low power high-performance multimedia computing through the reconfiguration of heterogeneous system modules.
Configware , Morphware from TU Kaiserlautern: Reconfigurable "hardware" is not really hard like classical hardware. It can be re-configured by structural code (configuration code) to be downloaded into the "hidden" RAM of such Morphware. Such structural code is fundamentally different from (classical) Software. Programming such reconfigurable platforms needs Configware instead. We may distinguish FPGAs (fine-grained morphware) from reconfigurable Data Path Arrays (DPAs: coarse-grained morphware): configured pipe networks.
Maxwell, FHPCA stands for the FPGA High Performance Computing alliance, it is an organizaton composed of Algotronix, Alpha Data, EPCC, Institute for System Level Integration, Nallatech, Xilinx, Scottish Enterprise.The FPGA High Performance Computing Alliance (FHPCA) is developing high-performance computing solutions using Field Programmable Gate Arrays(FPGAs) to deliver new levels of performance into the technical computing market. Hardware and software developed by the FHPCA have been used to build a large-scale demonstrator supercomputer called Maxwell. This is complemented by a campaign to raise industrial awareness and interest and to stimulate the market for the Alliance's members' commercial offerings.
DRC, modular coprocessor system
Many of the technological barriers to widespread use of reconfigurable computers have been overcome, and with standards-based reconfigurable interfaces and hardware plus a growing body of standard language compilers to support the technology, reconfigurable computing is poised to break through as a viable solution for a wide range of commercial and HPC applications.
Configurable Computing Lab, Research areas that are of Brigham Young University include: run-time reconfiguration, hybrid FPGA architecture, DSPs and FPGAs, and application-specific processors. The lab has a strong applications focus and has developed applications, demonstrations, and tutorials for many of the currently available FPGA platforms
RAGE, Reconfigurable Architectures Group, University of Glasgow
TRIPS, (The Tera-op, Reliable, Intelligently adaptive Processing System) is a revolutionary new microprocessor architecture being built in the Department of Computer Sciences at The University of Texas at Austin. The team's goal is to produce a scalable architecture that can accelerate industrial, consumer, embedded, and scientific workloads, reaching trillions of calculations per second on a single chip.
University of Ottawa, an alphabetical List of early Reconfigurable Computing Architectures
Wikipedia Read the definition of reconfigurable computing, containig an historical introduction about the subject starting from Gerald Estrin's work. It also cites the XPP and PiCoGA among the solutions that contributed to the reconfigurable computing renaissance of the last decade.
