A paper has from the MORPHEUS project was presented at the RAW 2008 conference.

Title: A Bandwidth Optimized SDRAM Controller for the MORPHEUS Reconfigurable Architecture
Authors: Sean Whitty, Rolf Ernst
Institute of Computer and Communcation Network Engineering
Technical University of Braunschweig, Germany

Abstract
High-end applications designed for the MORPHEUS computing platform require a massive amount of memory and memory bandwidth to fully demonstrate MORPHEUS's potential as a high-performance reconfigurable architecture.  For example, a proposed film grain noise reduction application for high definition video, which is composed of multiple image processing tasks, requires huge amounts of bandwidth due to its large input image size and real-time processing constraints. To meet these requirements and to eliminate external memory bottlenecks, a bandwidth-optimized DDR-SDRAM memory controller has been designed for use with the MORPHEUS platform and its Network On Chip interconnect. This paper describes the controller's architecture, including the interface to the Network On Chip and the two-stage memory access scheduler, and presents relevant experiments and performance figures.

Introduction
Reconfigurable architectures have opened the door to exciting new research directions and application domains, many of which have been heavily investigated in recent years. One such project, the ``Multi-purpose Dynamically Reconfigurable Platform for Intensive Heterogeneous Processing'' (MORPHEUS) project, is a European Integrated Project (IST 027342) which addresses innovative solutions for embedded computing based on a dynamically reconfigurable platform and a corresponding toolset~\cite{thoma:morpheus}. Its goal is to provide a flexible heterogeneous platform for HW/SW co-design via a unique architecture, composed of reconfigurable computing units of varying granulatity, as well as an integrated toolset that can be utilized to easily map and implement target applications.

The potential of the MORPHEUS platform will be demonstrated in several application domains. These include reconfigurable broadband wireless access and network routing systems, processing for intelligent cameras used in security applications, and film grain noise reduction for use in high definition video. The image-based applications have been shown to exhibit immense memory needs. For example, digital film applications require an image resolution of 2K \footnote{2K implies 2048x1536 pixels/frame, 30 bits/pixel, and 24 frames/s}, with data rates of up to 2.1 GiBit/s necessary for real-time operation. Higher resolutions of up to 4K and even 8K are on the horizon.

Satisfying such memory requirements is no easy task. SDRAM interfaces have long been a performance bottleneck, especially in network processing and multimedia applications. A recurring issue with modern DRAM architectures is relatively long access latencies. DDR-SDRAM and DirectRamBus DRAM (RDRAM) attempt to reduce these latencies by accessing several consecutive data words. This burst access technique, however, only lowers latencies and does not increase bandwidth. To this end, optimizations such as bank interleaving, which exploits the internal structure of DRAMs by accessing a second bank while another is busy, and request bundling, or the grouping or reads and write requests into groups, can be used to ensure maximum possible throughput across the SDRAM data bus.

Using such techniques to increase throughput naturally increases access latencies, as do complex access patterns. However, applications developed for the MORPHEUS platform are bandwidth hungry and can tolerate such latencies. Furthermore, the onboard ARM processor is used for control purposes and is not expected to make extended use of external memory. Therefore, a bandwidth-optimized memory controller, designed to serve the needs of high-performance reconfigurable architectures such as the MORPHEUS platform, is presented in this paper. For flexibility, the design also supports multiple service levels to reduce latency when necessary. After a brief overview of related work, the Architecture itself is defined, finally synthesis and performance results are examined.