A 2-day school on 8 & 9 October 2007 with lectures on advanced high level languages, methods, tools and architectures for concurrency, reconfigurability  and self-adaptivity (including techniques developed in AETHER and MORPHEUS). The abstract of the presentations is shown in this page.

Hardware Technologies for Adaptive and Self-Adaptive Computing S. Guyetant, CEA-LIST

Analysis of adaptability in computing, reconfigurable hardware provides advantages in adaptability. You can afford way complexer scheduling algorithms in HW than in SW. Reconfigurable architectures: APTIX, the MORPHEUS platform based on FlexEOS DREAM XPP. Definition of reconfiguration services. Examples: compression, allocation on different resources (PICOGA, FlexEOS, SOFTWARE). Conclusions: reconfigurable architectures provide more programmability and less overload for control and reconfiguration.

Coarse grain reconfigurable technology D. Picard, UBO

Analysis of available architectures (DSP,GPP, ASICS, FPGA, SOC, ASIC-accelerators, ASSP, customizable-processors (Tensilica, ARC) and reconfigurable architecture (DREAM architecture from ARCES). Motivation by comparing the Moore and Shannon law, technology improvement is not enough. DSP is modelled by DFG that can be implemented either in spatial or temporal domain. Special solutions add specialized functional units (Tensilica, ARC). VLIW and superscalar processors provide ILP at compile time or load time, Reconfigurable solutions provide parallelism at run time. DFG can be implementation on FPGA.
Reconfigurable architectures introduce the concept of instruction set metamorphosis. Reconfigurable architectures can be fine grained (LUT), coarse grained (data paths) or processor arrays.
Examples of reconfigurable architectures.
- The GARP architecture
- MOLEN approach using Xilinx Virtex-II, a Microcode based application
- the Xirisc architecture (ARCES)
- RDA reconfigurable data path array (Hartenstein)
- piperench architecture (Goldstein)
- Pact XPP (Becker Vorbach) array of 16 bit processing elements
- Morphosys from UC Irvine
- Tilera Tile processor and RAW are array of processors
Description of the DREAM small area architecture for crypto and  telecommunications applications based on PICOGA (DFG based)

SPEAR parallel application mapping tool  E. Lenormand TRT

General presentation about the tool for data streaming applications, it captures the application and the architecture providing an interactive design environment graph of the application. SPEAR helps mapping applications to architecture expressing regular streaming access. Graphs must be acyclic. SPEAR generates the code corresponding to the loops that represents I/O access to data, functions inside the loops are written in C they are mapped to tasks code inside tasks is encapsulated. It is possible to generate again the explicit C code of the SPEAR model.  There is a mapping of the loops to processors and data to memories to estimate performances. Insertion of communication, fusion and scheduling, performance simulation obtaining task and data parallelism. The tool computes a static scheduling based on production consumption relationships.

Design Methods and Architectures for Run-Time Adaptive Electronic Systems  M. Hübner UK

Design Methods and Architectures for Run-Time Adaptive Electronic Systems (Part I and II)
Trends of the ASIC/ASPP market from year 2000.
Introduction of the basic terminology about programmable, configurable, reconfigurable and dynamically reconfigurable systems.

A 2-day workshop on 10 & 11 October 2007 with presentations by external speakers and speakers from both projects. The abtracts of the presentations are shown in this page.

A Framework for Memory Based Mapping of Accelerated Function   A. Grasset  THALES

Nested loops often compose the computation intensive part of digital signal processing applications. Accelerating these loops kernels on specific hardware coprocessors bring gains in performances but lacks flexibility. Reconfigurable units provide a new trade-off in term of performances, cost and flexibility in System-on-Chip. However, programming these heterogeneous reconfigurable units is time consuming and error prone. Managing memory mapping and the addressing mechanism of multidimensional arrays is an issue on these kinds of systems due to their strong constraints on memory. In this context, high-level synthesis of functions on reconfigurable accelerators is interesting to reduce the time for application development. A design flow is developed in the MORPHEUS project in parallel to the MORPHEUS reconfigurable architecture. This flow covers the CPU programming and the high-level synthesis of the accelerated functions on reconfigurable units. The synthesis flow of the accelerated functions separates computation and communication issues, In the MORPHEUS platform, local buffers attached to three heterogeneous reconfigurable units are used for the communication. The talk describes a framework integrated in this flow which helps to manage communications and memory mapping related to the implementation of the accelerated functions on the reconfigurable units.

Process Networks on a Reconfigurable SoC   D. Picard UBO

The execution of an application on a reconfigurable SoC can be modeled as a set of coordinated processes. Some of these processes effectively run on the reconfigurable units, others are idle waiting for input data or synchronization conditions, while the remaining are suspended, and perhaps do not have hardware resources allocated. Processes need communication and synchronization mechanism to coordinate, but in some cases these mechanisms can be simple. It is the case if the application has been defined as a stream of structured data flowing into a pipeline of processes due to memory modes. In other cases, the system can be much complexer with typical synchronization problems appearing either at the application level and the system support level. The reconfigurability of the hardware even gives more importance to this question because race conditions can appear between the OS and the application behaviours. Thus, it is needed to develop a system methodology inside and outside the tool. This paper describes a pragmatic approach where the spatial process organization is specified separately from their behaviours. The organization allows to name processes and to bind them to a behaviour. The connectivity between processes defines the knowledge established in the system, and as a matter of facts, the communication links used to propagate this knowledge. This part of the system description is fixed in a model and grammar called AVEL.The talk presented the MORPHEUS architecture based on Dream-XPP-M2000, introducing the control data flow generator and presenting the generation of the CDFG from AVEL through the SyNE tool.

Prototype of a Dynamically Reconfigurable Network Node U. Pross TU Chemnnitz

Current high-end telecommunication networks like other digital technologies tools are subject to a rapid evolution. The requirements for these networks increase permanently in terms of transfer rate, security and quality. This evolution requires the development of new network standards or the adaptation of existing standards. On one hand standardization processes take a long time. Manufacturer of telecommunication equipment, who want early market presence, are often not able to wait until the end of the standardization process. Instead they have to implement standards which are not stable and might be adapted or changed in future. This causes a high business risk since a later adaptation of the standard may require a new implementation. However, the later the standard change occurs in the development cycle the more expensive a reimplementation and its new production are. On the other hand reimplementation can be caused by implementation mistakes as well. The risk of a reimplementation can be drastically reduced by the usage of reconfigurable technologies in integrated circuits. This presentation was about the implementation of a node which can be dynamically configured using the Ethernet protocol.

A System on Chip Decoder – a project oriented SoC design for education M. Kühnle University Karlsruhe

A good hardware design requires both competent theoretical as well as practical knowledge in the areas of architecture specification and design. While the theoretical background is given in many lectures, gaining practical knowledge is somewhat more difficult. Also connection points to research can be given more easily in such practical work by building a bridge to the latest research projects such as MORPHEUS, ect, where many similar development tasks exist. Also the application driven design is well covered by an audio system and can be well compared, although much less complex – to e.g. multimedia applications within MORPHEUS. Facing these facts, a laboratory has been established. Hardware and Software components have to be realized to build up a SoC for audio decoding. The goal of this laboratory is to make students familiar not only with practical aspects of HW/SW ASIC design flow. So, insight is given into different design methodologies and technologies starting from design space exploration through IP block integration to system verification. Also different design flows (FPGA based, standard cell based) are introduced. As used in MORPHEUS, the students are made familiar with the same state of the art development tools. Summarizing, the realization of the system provides a good base to study HW/SW Co-Design techniques in hands-on fashion. Although the content of the laboratory deals with complex topics (very close to project work), which require a good preparation and concentrated work of the students, the feedback was throughout very positive.

The M2000 FPGA – A New Direction in FPGA Architectures G. Pulini M2000

Almost all FPGA architectures use LUTs (lookup tables) to implement logic circuit functionality. What differentiates them is their interconnect architecture, and it has been apparent for many years that the cost, performance and power of deep submicron FPGAs are dominated by their interconnect architecture. M2000 has redefined FPGA interconnect architectures using a recursive, hierarchical interconnection scheme that scales much better than the grid-based interconnect architecture of traditional FPGAs. This produces much better logic density, resulting in better performance and lower power. This talk describes this novel interconnect architecture, and how it is used to provide flexible, high bandwidth connections between logic elements in large-scale FPGAs. We also discuss the functional components provided by the M2000 architecture, which include fast addition and multiplication as well as embedded dual port memories. Finally, the support for dynamic reconfiguration is discussed along with example applications.

Portable Synthesis in MORPHEUS L. Lagadec UBO

MORPHEUS promotes the transparent use of heterogeneous reconfigurable resources in system on chip. Given the variety of reconfigurable architectures and low level specification languages, it is necessary to use a robust methodology to isolate the application description languages from the possible targets. The WP2 consortium has adopted the idea of a common format for algorithm description that could be used as a crosspoint for sources and targets. This format is a kind of Control Data Flow Graph address by an application programming interface. An input language compiler can then generate processing description to this API producing library or files for the synthesis tools. As for now several tools output CDFG description: Cascade from CriticalBlue, SPEAR from Thales TRT, SpecEdit from Alcatel Lucent, AVEL (concurrent process system description environment). This talk presents the WP2 flow from the CDFG down to the synthesis over IPs and especially over MP2000 IP. This goes through defining the CDFG structure (formal description in EXPRESS) and its associated tools (rules checker, interchange via STEP files). Also transformations performed over specific CDFGs are introduced: partitioning, mapping ordering, scheduling and synthesis.

On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems M. Hübner University Karlsrühe

The progress in hardware technologies for implementing portable, low power and low cost electronic systems for consumer products has been major the last years. The complexity of embedded systems will further increase at a rate which is not met by the development of advanced CAD tools for managing the large design space. This will likely lead to increased design problems regarding system implementation, test and verification. This talk presents how the design complexity can be managed at the hardware level by integrating self-adaptive characteristics, and how the trade-off in performance and flexibility can be optimized to fulfil all application requirements while reducing the design complexity.

XPP-III Basics and SoC Integration E. Schüler PACT

Application and market requirements are driving the deployment of the new architectures when existing solutions cannot fulfil the actual needs. “Reconfigurable Computing” is one answer to the ever increasing application requirements. In addition to the well understood FPGAs, also coarse grain architectures are now ready to be adopted into the computing mainstream. During this session we present the third generation of XPP, one of the first coarse grain reconfigurable architectures. XPP-III is built from an array of ALUs and RAMs with a programmable interconnect. The array is configured statically and data to be processes streams through the network of operators. The programming model is based on direct mapping of data flow graphs to the array. Larger algorithms are partitioned into several graphs which are dynamically reconfigured. This way of processing provides a very high degree of parallelism for algorithms such as FFTs, filter, raw pixel processing etc. In addition to the reconfigurable array new VLIW-similar processing elements are tightly coupled to the array. Those processing elements provide parallelism for algorithms which are sequential by nature and where a large number of decisions must be made. Examples are parsers, protocol handling, arithmetic decoders etc. The combination of both types of processing elements extends the application space of the reconfigurable array substantially. Even as important as the raw processing power is the integration into SoC and the memory hierarchy. We present a framework of building blocks and a network for streaming data that allows flexible integration into any SoC and memory architecture. Two examples are shown, the integration in the MORPHEUS SoC and the XPP-3C accelerator chip. The programming concept and the native tools and APIs to program this versatile architecture are shown. The complete XPP-III platform will be available in a SystemC based software simulator which allows not only standalone simulation of the XPP but also the integration into a SoC simulation environment which will be demonstrated in the MORPHEUS project.

High Speed DDR-SDRAM Memory Controller for the MORPHEUS Platform S. Whitty TU Braunschweig

Applications designed for the MORPHEUS platform may require a massive amount of memory, as well as sufficient bandwidth, to fully demonstrate MORPHEUS’ potential as a high performance reconfigurable architecture. For example, the film grain noise reduction application, which is composed of multiple image processing tasks, requires massive amounts of bandwidth due to its real time requirements. To meet these requirements and to eliminate external memory bottlenecks, a high bandwidth DDR SDRAM memory controller (CMC) has been designed for use in the MORPHEUS platform.

Quick Integration of High Level Tools in MORPHEUS: The case of SpecEdit C. Teodorov UBO

MORPHEUS promotes the transparent use of heterogeneous reconfigurable resources in SoC. Given the variety of reconfigurable architectures and low level specification languages, it is necessary to use a robust methodology to isolate the application description languages from the possible targets. The WP2 consortium has adopted the idea of a common format for algorithm description that could be used as a cross-point for sources and targets. This format is a kind of Control Data Flow Graph (CDFG) addressed by an application programming interface (API). An input language compiler can then generate processing description to this API producing library of files for the synthesis tools. The aim of this paper will be to demonstrate the method we follow to integrate new environments to MORPHEUS.The tool SpecEdit is build around a formalism called ADeVA (Advanced Design and Verification of Abstract Systems) from Alcatel Lucent. Its aim is to allow specifying and verifying complex state machines from simple composition of processes interacting with the environment. This formalism has been represented as a set of Smalltalk 80 classes that have been derived from an XML output of SpecEdit. As a practical result it is now possible to generate CDFG representing the SpecEdit specification. The example of a traffic light controller is used to illustrate this transformation.

Mapping to a Reconfigurable IP L. Lagadec UBO

Integrating external components in a system on chip is a challenge at both the chip level and the software tool chain. In the MORPHEUS project, a generalized approach has been developed using CDFG as a computation representation and tools dedicated to the mapping of computations to components. In this paper, we describe two different techniques used to integrate respectively the PiCoGA array and the XPP-IIb datapath in the tool chain. Each technique based itself on the component programming interface and documentation, giving varying degrees of knowledge and control over it, and, importantly, being more or less difficult to implement. The results demonstrate the feasibility of the concept of a unified tool chain. Such results will allow SoC designers to evaluate how effective and complex the integration of a component into the tool chain is, and, for the developer of a component proposed for integration, which level of documentation or access to the component it the most competitive for a prospective SoC designer makes.

Other informatoon is also available on  the ALARI WEB site.