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Objectives The goal of this MORPHEUS work
package is to provide a
semi-automatic tool platform for reconfigurable computing
supporting a fully integrated and entire design process rather than
isolated parts.
Furthermore, we are interested in
having realistic albeit ambitious goals. Developing the entire platform
from the beginning may pose a high risk within the time frame and the
personnel constraints of a single work package. We intend to use, when
possible, existing software and enhance it appropriately to develop
tools for the reconfigurable components. The work proposed by the
current proposal intends to bridge the gap between what is readily
available and what is needed to develop a fully integrated,
semi-automatic reconfigurable workbench. Challenges The design flow of a global
application implies many actors from algorithm specialists to
implementation designers. The global challenge for the tools provided
to these actors is to allow them to take full benefit of their
expertises. Toolset position within a global approach A global design flow can be
considered at 2 levels: MORPHEUS will mainly address this
lower level approach. MORPHEUS tools will thus first address the
MORPHEUS architecture, which is mainly composed of a host processor,
combined with a fine grain and coarse grain reconfigurable array.
However, we will employ techniques transposable to most architectures. The project will not focus on the
back-end part (very specific of the hardware, like logic synthesis,
place and route, bit-stream generation, etc). n
n
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The top border of MORPHEUS tools can be defined as the output of "high
level compilers" (HLC) whose role would be to produce the mapping of an
application description towards a roughly defined architecture. This
mapping would either be done automatically or through an interactive
design-space exploration [LEN03][VUL04]
[ZHA00].The development of these HLC tools is out of the scope of the project: it should typically be addressed in further studies (in FP6 IST call 5 for example) and thus their output shall be considered as the potential input for the tools developed in this project. The log file for generating the configuration dependency graph has to be specified from bottom up view. Content of this log-file has to be the schedule of the different tasks and the resulting allocation of the hardware resources. The results of this specification are the requirements on log files of future (NOT part of MORPHEUS!) high-level compilers. Moreover, the existing model-based verification techniques/tools has to be extended in a manner, that dynamic reconfiguration schedules as well as data dependencies are an additional input for the verification tool and the functionality/task models to be formally verified, including the derived constraints/properties to be verified. These constraints/properties should be derived from the log files of the high-level compiler and the generated configuration-dependency graph. This input therefore consists in the description of a rough mapping of the application on an architecture. This mapping may possibly be composed of the three following partitioned parts (Figure 1): • reconfigurable function (spatial) descriptions combined with • processor-mapped sequential descriptions and • configuration state descriptions (characteristics and dependencies of application modes). The languages necessary for these descriptions will have to be defined or chosen among possible candidates identified. One can already mention as reasonable candidates for the three different inputs from high level compilation: • Set of Tasks bound to protocols: tasks are CDFGs to be bound to protocol. This opens the way to possible connection to many high level design tools like SIMULINK, etc. • Task activations generated/extracted from control flow (dynamic configuration description):Process Networks (CSP-like, stream computations, object-oriented, etc.) • Programmable flow that includes hardware process activations: processor mapped sequential descriptions (C language, etc.) On the other end, the bottom border of the set of proposed tools can be defined as the input of the "back end tools", such as logic synthesis tools, place & route and bit-stream generation. As stated above, we consider that these tools are not in the scope of this work package since they are considered as either available on the market or provided with the architecture (even MORPHEUS architecture). Therefore, the outputs of the proposed tools developed in this work package are a hardware description of the spatial implementation (in VHDL for fine grain and adequate description for coarse grain possibly based on open models of different blocks of architecture) and the software description in C language plus possible complementary micro-code when necessary.  Figure 1 MORPEUS tools Another way of viewing the design flow is to distinguish between design time components and runtime components. The former, such as spatial computation, concern tools preparing static code while the latter, such as dynamic control design and sequential code compilation, concern tools preparing dynamic management. The low level spatial design tools consist of either COTS environments like ISE XILINX, PACT, M2000, either tools developed in the project to optimise the integration.
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