This edition of the Unicad Workshop has been enriched by a presentation about reconfigurable computing focussing on the PiCoGA architecture and a related demostration. During the presentation the MORPHEUS project was indicated as the most important exploitation of the PiCoGA architecture outside the company. After introducing the contents of MORPHEUS, the first feedback from the community of designers within ST indicates that some of them are willing to try also the others reconfigurable processing elements that are proposed within MORPHEUS.

A presentation entitled:  “Configurable data-path PiCoGA“ was proposed.

Contents of the presentation

In this presentation the MORPHEUS project was introduced as the most important exploitation of the PiCoGA architecture outside ST. The architecture of MORPHEUS was also explained in detail, compatibly with the status of development of the project. PiCoGA (Pipelined, Configurable Gate-Array) is a run-time reconfigurable hardware device that enhances the performances of a hybrid architecture based on a processor core to which it is coupled. It has been designed at ARCES from cooperation between University of Bologna and ST. Performance can be significantly affected by extending the ISA using the run-time configurable core PiCoGA. The PiCoGA is an array of rows, each row is connected to the other rows and to the register file and represents a possible stage of a customized pipeline that is controlled by a dedicated configurable control unit. The control unit can force the array to hold internal state and supports implementation of high level language constructs such as for/while loops. Each row is composed of 16 Reconfigurable Logic Cells (RLC) and a configurable horizontal interconnect channel. A RLC contains two 4-inputs, 2-outputs look-up tables, four registers and an internal loop-back connection to easily implement accumulators. To minimize the reconfiguration time, the PiCoGA includes a 4-layer cache of configurations requiring one clock cycle to switch among them. While one layer is computing, reconfiguration of other layers is allowed. The design flow approach relies on identification of the computational kernels to map on the PiCoGA. Kernels are determined by profiling, using standard processor compilation and simulation tools. An identified kernel is re-written utilizing Griffy-C. It is a DFG description language based on a restricted subset of ANSI C syntax enhanced with some extensions to handle variable resizing and registers allocation inside the PiCoGA: differences to other approaches are in the fact that Griffy-C is aimed at the extraction of a pipelined DFG from standard C and its mapping over a gate-array that is also pipelined by explicit stage enable signals.