MORPHEUS project home page

MORPHEUS stands for Multi-purpOse dynamically Reconfigurable Platform for intensive HEterogeneoUS processing. The project, coordinated by Thales, is funded by the EU under contract IST-4-027342 for the duration of 45 months (01/06 - 09/09). The project flyer illustrates a comprehensive overview about the different research areas and working groups.

MORPHEUS addresses innovative solutions for embedded computing based on a dynamically reconfigurable platform and adequate tools. The large-scale deployment of embedded systems demands computing performance, cost-efficient development, functional flexibility and sustainability. Current architectures solutions are out of breath and current design tools do not support the time-to market needs.

MORPHEUS develops a global solution based on a modular heterogeneous SoC platform that provides the disruptive technology of dynamically reconfigurable computing completed by a software oriented design flow and a consistent toolset. These “Soft Hardware” architectures enable huge computing density improvements (GOPS / mm² ), reuse capabilities, flexibility and time to market thanks to a convenient programming toolset. MORPHEUS aims to establish the European foundation for a new concept of flexible “domain focused platforms”, positioned between general purpose flexible HW and general purpose processors and providing breakthroughs in performance and cost-effectiveness to embedded computing systems.

The solution will be validated by a set of four complementary test cases: Broadband wireless access, Network routing, professional video filters and intelligent cameras. The dissemination through a silicon demonstrator and a supporting toolset, which are both an essential baseline for following commercial products, is completed by widespread information (publications; the MORPHEUS book ) to address the communities of electrical engineering and computer science.

PROJECT RESULTS

The MORPHEUS concept has been evaluated and proven in the project's time frame by the realization of a specific demonstration instance of the platform's capabilities resulting in the successful production of a MORPHEUS prototype. The chip has been manufactured in ST CMOS 90nm technology. Figure 1 shows a die picture of the morpheus chip. The chip shows very nicely the three HRE devices and their different grains (the Architecture section details the logical structure of MORPHEUS). On the bottom right the coarse grain 16-bit ALU array of the XPP-III can be seen. The top right shows the mix-grained 4-bit DREAM array structure. The top left contains the fine grain (1-bit) embedded FPGA macro. The black boxes illustrate on-chip memory whereas the rest is occupied by ARM, communication infrastructure and periphery. The test-chip was succesfully verified at ST premises.

Figure 1: Photo of the MORPHEUS Chip

Table 1 shows a final report of the MORPHEUS chip performance, resuming maximum frequencies reachable by the system and the chip power consumption at the reference supply voltage of 1V. Since Morpheus supports dynamic frequency scaling, the dynamic power consumption of the MORPHEUS chip has been expressed in mW/MHz and dividing the contributions of the 4 clock islands (Main domain including communication, control and synchronization, DREAM, eFPGA, XPP). Further results have been published at CICC 2009.

	AREA [mm²]	STATIC POWER [mW]	DYNAMIC POWER [mW/MHz]	MAX FREQUENCY [MHz]	MAX POWER [mW]
Main DOMAIN (Communication/Synchronization)	37		2.4	240	576
DREAM	18		2.1	160	336
EFPGA	12		0.8	140	112
XPP	43		7.6	160	1216
TOTAL	110	235			2475

Table 1: MORPHEUS silicon prototype final report

The corresponding demonstration board was developed at Thomson, Hannover. The system (Figure 2) has been successfully started up in July 2009. The board features

MORPHEUS IC
Ethernet Phy and connector
Extension Board Connector
SRAM and SRAM debug connector
Two RS232 interfaces
Clock-circuitry and on-board power supply
General purpose IOs,status LEDs,reset buttons and configuration switches

Figure 2: On the left: The MORPHEUS chip and board; On the right: The SRAM access extension board.

The MORPHEUS toolset has also been released, including management of dynamic reconfiguration thanks to a combination of the Delft University MOLEN implementation on ACE COSY compiler and drivers implemented within the eCOS RTOS by Universit�t Karlsruhe and THALES. Netlist generation for the configuration of the FlexEOS eFPGA from high level C-based description was demonstrated based on CriticalBlue CASCADE compiler, THALES SPEAR data mapping tool and MADEO tool by Universit� de Bretagne Occidentale. Alcatel-Lucent and Universit�t Chemnitz work on the SpecEdit tool are also available.

The evaluation of the MORPHEUS technology by running the identified test cases came up with several important aspects. The concept of an integrated toolset demonstrated the importance of the achieved high gain in productivity and re-use with a low requirement of hardware knowledge. This allows to find out which kinds of algorithm matches best with which reconfigurable technology of the processing units of the MORPHEUS chip. Experience with application mapping in MORPHEUS showed often that simple design decisions at early design stages later on will have strong impact on the efficiency of the chosen platform. Another important aspect is the design methodology. Implementation productivity strongly depends to the availability of design tools and appropriate methodologies. The working group "Methodologies and tools" implemented a homogeneous system view and programming paradigm according to that request. As a result, the effort to map an algorithm on the MORPHEUS platform is comparable than the mapping on state of the art technology. This is a very positive result when recalling the heterogeneous nature of the architecture.