NEW REQUIREMENTS

Data intensive processing is receiving renewed attention, due to rapid advancements in multimedia computing and high-speed telecommunications. Many of these applications demand very high performance circuits for computationally intensive operations, often under real-time requirements. Furthermore, their computation power appetite tends to soar faster than Moore’s law.

Figure 1: Moore’s law, algorithm complexity and Embedded Software evolution

Moreover, embedded computing (“computing everywhere”) means computing chips dedicated by market while at the same time developments costs are exploding. This results in an increasing need of flexibility not only at the program level (by software) but also at the chip level (by hardware).

So, combining flexibility and performance is now a key enabler for embedded computing platforms. This project aims to pave the way for providing a global European solution offering these capabilities.

CURRENT SOLUTIONS ARE REACHING LIMITS

• Current computing solutions are out of breath for embedded systems: challenge of computing density and low power
• Current development and programming tools do not provide the required productivity

On one hand, the performances of embedded platforms with fixed architectures and fixed software optimisations, in spite of the continuous increase in processors’ speed, are, not surprisingly, lagging behind. Processors efficiency is more and more impaired by the memory bandwidth problem of traditional von Neumann architectures.

On the other hand, the conventional way to boost performance through Application Specific Integrated Circuits (ASIC) lacks the flexibility of programmable processors and suffers from sky-rocketing manufacturing costs (requiring high volumes to be amortized) and long design development cycles. In the nanometre era, increasing non recurrent engineering costs could relegate System On Chip (SOC) to very few high volume products unless some standardization process is undertaken.

Modern Field Programmable Gate Arrays (FPGA) can implement an entire SOC [BOL02], but at the cost of large silicon area and high power consumption. So, if they bring the maximum of flexibility with their fine grain architecture, they fail in providing cost-effectiveness data flow implementation due to the lack of support for a computing approach.

Moreover, a huge design productivity issue is raised by the difficulty of embedding algorithms on complex massively parallel architectures, while defining the processing architecture, under time to market pressure. Defining a programming paradigm for reconfigurable architectures is a difficult problem, where embedded software (SW) programming and Computer Aided Design (CAD) technologies must cooperate [SCH04]. Current CAD tools have synthesis capabilities that don’t reach the abstraction level required to handle complex hardware implementation.

RECONFIGURABLE COMPUTING

• Reconfigurable computing (RC) offers a highly parallel, scalable (in performance and sustainability) solution providing hardware (HW) performance combined with SW flexibility and low cost of ownership.
• It must be associated with high abstract level tools for generic SOC platforms.

One chief advantage brought by RC, whose FPGA mentioned above are only a part, is that such a special-purpose hardware can be built as SW by programming the configuration of the array. When running, it performs like a massively parallel computer. When no longer required, it can be replaced in the same way as new software is loaded on a CPU. This advantage becomes predominant when looking to the increasing cost of development and ownership of conventional SOCs (Figure 3). Platform based SOC, by providing reuse capabilities, is a first but incomplete response to this issue.

RC platforms offer the opportunity to design a standard HW platform which can be specialized [CAM03] [CAR99] for application at run time. The ability of customizing an architecture to match the computation requirements of an application or the evolution of its specifications after fielding has demonstrated significant improvements in computational efficiency and cost-effectiveness compared with ASIC solutions or general purpose processing architectures. Flexibility is a major driver in the utilisation of RC. RC exhibits a very competitive trade-off between flexibility, power and performance [SEK04] [SMI01].

Whilst general purpose processors are meeting diminishing returns with increased clock rates, RC is emerging as a new paradigm, able to provide large-scale spatial designs of high performance for a diversity of applications. This trend toward “Soft Hardware” architectures is illustrated by Figure 2.

So, the technology context is now right for exploring and harnessing its full potential in domains particularly amenable to spatial computations like those addressed by MORPHEUS.

Reconfigurable technology is a key enabler for more and more electronic products, also in medium and large volume. In fact, with the advent of middle and coarse grain array structures, a specialization is possible. The key issue is to identify the right RC platform for such or such domain or application.

Reconfigurable technology is a key enabler for more and more electronic products, also in medium and large volume. In fact, with the advent of middle and coarse grain array structures, a specialization is possible. The key issue is to identify the right RC platform for such or such domain or application.

MORPHEUS PROJECT AMBITION

From a business perspective, embedded systems are facing tough cost-effectiveness issues: the mitigation of increasing developments costs of silicon platforms dedicated by markets (customer-centric development with stringent time to market and short lifecycle constraints) is imperative: the customisation after fabrication by SW techniques promises to give the response provided that challenges in architecture and design tools are overcome. The first ambition of this project is to provide best of class solutions in these domains and to support these key markets for Europe.

Existing commercial products (mainly low architecture level FPGA from United-States vendors, completed by some Intellectual Property products) bring limited benefits in combining flexibility (field programmability) and efficiency (computing density, development time) due to the lack of hybrid architecture and late binding capabilities. On the other hand, cutting edge research programmes in Europe and R&D programmes in the US demonstrate decisive improvements through dynamic reconfiguration on coarse grain architectures provided that ambitious associated tools exist. Thus, MORPHEUS project ambitions to provide a new type solution summarized in Figure 4.

The figure shows the position of the MORPHEUS platform in the range of computing solutions for Embedded Systems, between generic, programmable but inefficient General Purpose Processors (GPP), optimised but inflexible ASIC and flexible generic but inefficient FPGA.

APPLICATIONS

• Broadband Wireless Access Systems, where IEEE 802.11a and 802.16-2004 implementation on same SOC is expected to lead to important silicon area savings and design time improvement,
• Network routing systems, where RC-enhanced network processors designs are poised to make an impact on future packet-processing systems in so-called active networks.
• Professional video, where it is expected that typical image processing operations can be mapped very efficiently on coarse grain reconfigurable architectures 
• Homeland security, where improved detection and identification require Intelligent camera systems where algorithms require sustained performance in the tens of GFLOPS while providing cost-effectiveness and sustainability