News headline
Application
to the ICT 2008 event on 25-27 November 2008 in Lyon, France
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MORPHEUS presentation at VLSI SoC 2008 conference
October 13-15 Rhodes Island, Greece.
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MORPHEUS-AETHER
Autumn
School and Workshop Oct 7-9 2008 in Lugano, Switzerland.
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RAW
2008,15th Reconfigurable Architectures Workshop. April 14-15, 2008.
Miami, Florida, USA.
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MORPHEUS at DATE 2008 Munich, Germany 10-14 March
2008.
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Two papers at SYMPA08 conference. Fribourg,
Switzerland, Feb. 11-13 2008.
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Welcome to the MORPHEUS reconfigurable computing
project
(IST-4-027342) website (release 2.0, November 5 2008)
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Next release (2.1) will be
on-line on November-30-2008.
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number  since Jan-1-2008 (WebCounter).
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SUMMARY OF THE PROJECT
Project Acronym:
MORPHEUS
Project Reference: 027342
Start Date: 2006-01-01
Duration: 42 months
Contract Type: Integrated Project
End date: 2009-06-30
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MORPHEUS stands for Multi-purpOse dynamically
Reconfigurable Platform for intensive HEterogeneoUS processing. See the
project Flyer.
MORPHEUS addresses innovative solutions for embedded computing based on
dynamically reconfigurable platform and tools. The large-scale
deployment of embedded systems demands computing performance,
cost-efficient development, functional flexibility and
sustainability. Current architectures solutions are out of breath
and current design tools do not support the time-to market needs.
MORPHEUS develops a global solution based on a modular heterogeneous
SOC platform that provides the disruptive technology of dynamically
reconfigurable computing completed by a software oriented design flow
and a consistent toolset. These “Soft Hardware” architectures enable
huge computing density improvements (GOPS / mm2 ), reuse capabilities,
flexibility and time to market thanks to a convenient programming
toolset. MORPHEUS aims to establish the European foundation for a new
concept of flexible “domain focused platforms”, positioned between
general purpose flexible HW and general purpose processors and
providing breakthroughs in performance and cost-effectiveness to
embedded computing systems.
The solution will be validated by a set of four complementary test
cases: Broadband wireless access, Network routing, Professional video,
Homeland security. The dissemination through silicon offer and
supporting tools (baseline for further commercial products) will be
completed by specific training and broad information to address the
necessary cultural change.
PROJECT FIRST RESULTS
The reference application platforms are ready and have been
demonstrated, notably the FlexFilm FPGA-based de-noise video platform
by Universität Braunschweig and Thomson, the Terapix FPGA-based
platform by THALES. These platforms were also presented at DATE
conference (10-14 March 2008).
The architecture of the MORPHEUS chip is finalized. It notably includes
ARM9 controller, 3 various-grain reconfigurable units (M2000 eFPGA,
ARCES PICOGA and PACT XPP), software-based dynamic reconfiguration, NoC
based interconnect and possibility for Dynamic Frequency Scaling. HDL
development now permits to tackle with block level place and route
activity and global floorplan.
Fig: The MORPHEUS chip
architecture
The chip floorplan is now ready for main blocks and for the top level.
The foundry of the chip is planned to be performed through IMAG CMP
techno access to ST technology.
The first release of the toolset has been demonstrated, including
management of dynamic reconfiguration thanks to a combination of the
Delft University MOLEN implementation on ACE COSY compiler and drivers
implemented within the eCOS RTOS by Universität Karlsruhe and
THALES. Design of configuration of M2000 eFPGA from high level C-based
description was demonstrated, based on CriticalBlue CASCADE compiler,
THALES SPEAR data mapping tool and MADEO tool by Université de
Bretagne Occidentale. Alcatel-Lucent and Universität Chemnitz work
on the SpecEdit tool are also available.
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