KEY REQUIREMENTS FOR FUTURE EMBEDDED SYSTEMS

Data intensive processing is receiving renewed attention, due to rapid advancements in multimedia computing and high-speed telecommunications. Many of these applications demand very high performance circuits for computationally intensive operations, often under real-time requirements. Furthermore, their computation power appetite tends to soar faster than Moore’s law (Figure 1).

Figure 1: Moore’s law, algorithm complexity and Embedded Software evolution

Moreover, embedded computing (“computing everywhere”) means dedicated computing chips dedicated for each product while at the same time development costs are exploding. This results in an increasing need of flexibility not only at the program level (by software) but also at the chip level (by hardware). So, combining flexibility and performance is now a key enabler for embedded computing platforms. This project aims to pave the way for providing a global European solution offering these capabilities.

LIMITATIONS OF CURRENT SOLUTIONS

On one hand, the performances of embedded platforms with fixed architectures and fixed software optimisations, in spite of the continuous increase in processors’ speed, are, not surprisingly, lagging behind. Processors efficiency is more and more impaired by the memory bandwidth problem of traditional von Neumann architectures. On the other hand, the conventional way to boost performance through Application Specific Integrated Circuits (ASIC) lacks the flexibility of programmable processors and suffers from sky-rocketing manufacturing costs (requiring high volumes to be amortized) and long design development cycles. In the nanometre era, increasing non recurrent engineering costs could relegate System On Chip (SOC) to very few high volume products unless some standardization process is undertaken.

Modern Field Programmable Gate Arrays (FPGA) can implement an entire SOC , but at the cost of large silicon area and high power consumption. So, if they bring the maximum of flexibility with their fine grain architecture, they fail in providing cost-effectiveness data flow implementation due to the lack of support for a computing approach.

Moreover, a huge design productivity issue is raised by the difficulty of embedding algorithms on complex massively parallel architectures, while defining the processing architecture, under time to market pressure. Defining a programming paradigm for reconfigurable architectures is a difficult problem, where embedded software (SW) programming and Computer Aided Design (CAD) technologies must cooperate . Current CAD tools have synthesis capabilities that don’t reach the abstraction level required to handle complex hardware implementation. In short, the limitations of current solutions are:

• Challenges about computing density and low power while sustaining flexibility cannot be met.
• Current development and programming tools do not provide the required productivity

RECONFIGURABLE COMPUTING

One chief advantage brought by RC, whose FPGAs - mentioned above - are only a part, is that such a special-purpose hardware can be built as SW by programming the configuration of the array. When running, it performs like a massively parallel computer. When no longer required, it can be replaced in the same way as new software is loaded on a CPU. This advantage becomes predominant when looking to the increasing development costs of conventional ASICs. Figure 3 shows that with technology scaling more and more revenue must be acquired to cover the Process cost (nowadays 45 nm and below) of these devices, which is becoming unaffordable or too risky in many cases. ASICs, providing reuse capabilities, are a first but incomplete response to this issue.

RC platforms offer the opportunity to design a standard HW platform which can be specialized for application at run time. The ability of customizing an architecture to match the computation requirements of an application or the evolution of its specifications after fielding has demonstrated significant improvements in computational efficiency and cost-effectiveness compared with ASIC solutions or general purpose processing architectures. Flexibility is a major driver in the utilisation of RC. RC exhibits a very competitive trade-off between flexibility, power and performance .

Whilst general purpose processors are meeting diminishing returns with increased clock rates, RC is emerging as a new paradigm, able to provide large-scale spatial designs of high performance for a diversity of applications. This trend towards “Soft Hardware” architectures is illustrated by Figure 2. So, the technology context is now right for exploring and harnessing its full potential in domains particularly amenable to spatial computations like those addressed by MORPHEUS.

Reconfigurable computing is a key enabling paradigm for platform sustainability through flexibility. It offers a highly parallel, scalable (in performance and sustainability) solution providing hardware performance combined with software flexibility and low cost of ownership, while it must be associated with high abstract level tools for generic SOC platforms. As a result, reconfigurable technology is a key enabler for more and more electronic products, also in medium and large volume. In fact, with the advent of middle and coarse grain array structures, a specialization is possible. The key issue is to identify the right RC platform for such or such domain or application.

Figure 2: Computing technology waves (Nick Tredennick)

Figure 3: The Return on Investment issue (EDN04)

MORPHEUS PROJECT AMBITION

From a business perspective, embedded systems are facing tough cost-effectiveness issues: the mitigation of increasing developments costs of silicon platforms dedicated by markets (customer-centric development with stringent time to market and short lifecycle constraints) is imperative: the customisation after fabrication by SW techniques promises to give the response provided that challenges in architecture and design tools are overcome. The first ambition of this project is to provide best of class solutions in these domains and to support these key markets for Europe.

Existing commercial products (mainly low architecture level FPGA from United-States vendors, completed by some Intellectual Property products) bring limited benefits in combining flexibility (field programmability) and efficiency (computing density, development time) due to the lack of hybrid architecture and late binding capabilities. On the other hand, cutting edge research programmes in Europe and R&D programmes in the US demonstrate decisive improvements through dynamic reconfiguration on coarse grain architectures assuming that ambitious associated tools exist. Thus, the MORPHEUS project ambitions to provide a new type solution summarized in Figure 4 .

Figure 4 shows the position of the MORPHEUS platform in the range of computing solutions for Embedded Systems, between generic, programmable but inefficient General Purpose Processors (GPP), optimised but inflexible ASIC and flexible generic but inefficient FPGA.